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| ? 2008 microchip technology inc. advance information ds39919a-page 1 pic24fxxkaxxx 1.0 device overview this document defines the programming specifications for the pic24fxxkaxxx family of 16-bit micro- controller devices. this is required only for developing programming support for the pic24fxxkaxxx family. users of any one of these devices should use the development tools that are already supporting the device programming. the programming specifications are specific to the following devices: ? PIC24F08KA101 ? pic24f16ka101 ? pic24f08ka102 ? pic24f16ka102 ? pic24f04ka200 ? pic24f04ka201 2.0 programming overview of the pic24fxxkaxxx family this section describes the two methods of programming the pic24f xxkaxxx family of devices: ? in-circuit serial programming? (icsp?) ? enhanced in-circuit serial programming (enhanced icsp) the icsp programming method is the most direct method for programming the device. however, it is also the slower of the two methods. it provides native, low-level programming capability to erase, program, and verify the device. section 3.0 ?device programming ? icsp? describes the icsp method. the enhanced icsp method is a faster method, which takes advantage of the programming executive as illustrated in figure 2-1. the programming executive provides the necessary func tionality to erase, program and verify the device through a command set. the com- mand set allows the programmer to program the pic24fxxkaxxx devices without having to deal with the low-level programming protocols of the device. section 4.0 ?device programming ? enhanced icsp? describes the icsp method using the programming executive. figure 2-1: programming system overview for enhanced icsp? method 2.1 power requirements all devices in the pic24fxxkaxxx family are 3.3v supply designs. the core, the peripherals and the i/o pins operate at 3.3v. the device can operate from 1.8v to 3.6v. 2.2 entering programming mode overview there are two methods of entering the programming mode (either icsp or enhanced icsp): ? low-voltage icsp entry when the mclr /v pp /ra5 pin is used as mclr by applying v ss on mclr (low-voltage entry), the device gets reset, and on applying the program- ming mode entry sequence on the pgcx and pgdx pins, the device enters the programming mode. ? high-voltage icsp entry to enter the programming mode, if the mclr function of the mclr /v pp /ra5 pin needs to be disabled or is already disabled, a voltage v ihh should be applied on v pp (high-voltage entry). this is equivalent to applying v ss on mclr ; the device gets reset. on applying the programming mode entry sequence on pgcx and pgdx pins, the device enters the programming mode. programmer programming executive on-chip memory pic24fxxkaxxx pic24fxxkaxxx flash progr amming specifications
pic24fxxkaxxx ds39919a-page 2 advance information ? 2008 microchip technology inc. 2.3 pin diagrams figure 2-2 provides the pin diagrams for the pic24fxxkaxxx family. table 2-1 provides the pins that are required for programming (indicated in bold letters in figure 2-2). refer to the appropriate device data sheet for pin descriptions. figure 2-2: pin diagrams pic24xxkax01 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20-pin spdip, soic mclr/ v pp pgc2 pgd2 pgd1 pgc3 pgd3 pgc1 v dd v ss pic24fxxka102 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin pdip, soic mclr / v pp v ss v dd pgd1 pgc1 pgd3 v dd v ss pgc3 pgd2 pgc2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14-pin spdip, soic mclr/ v pp pgc2 pgd2 pgc3 pgd3 v dd v ss pic24f04ka200 28-pin qfn 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 pic24fxxka102 5 4 v ss pgd1 pgc1 pgd2 pgc2 v dd pgc3 pgd3 mclr / v pp v dd vss pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 3 table 2-1: pin descriptions (during programming) 2.4 memory map the program memory map extends from 000000h to fffffeh. code storage is located at the base of the memory map, and supports up to 5.5k instruction words (about 16 kbytes). table 2-3 provides the program memory size and number of program memory rows present in each device variant. the pic24fxxka1xx family devices have an on-chip data eeprom. this data eeprom is mapped to the program memory area from location 7ffe00h to 7ffffeh. table 2-4 provides the data eeprom size and the number of rows present in each device variant. the erase operation can be done on one word, half of a row or one row at a time. the program operation can be done only one word at a time. locations, 800000h through 8007feh, are reserved for executive code memory. this region stores the programming executive, the debugging executive and the diagnostic words. the programming executive is used for device programming, and the debug executive is used for in-circuit debugging. this region of memory cannot be used to store user code. the device configuration registers are implemented from location f80000h to f80010h, and can be erased or programmed one register at a time. table 2-2 provides the implemented configuration registers and their locations. locations, ff0000h and ff0002h, are reserved for the device id registers. these bits can be used by the programmer to identify the device type that is being programmed. see section 6.0 ?device id? for more information. the device id registers read out normally even after code protection is applied. figure 2-3 depicts the memory map for the pic24fxxkaxxx family variants. table 2-2: config uration register locations table 2-3: code memory size table 2-4: data eeprom memory size pin name during programming pin name pin type pin description mclr /v pp mclr /v pp p programming enable v dd v dd p power supply v ss v ss pground pgcx pgc i programming pin pair: serial clock pgdx pgd i/o programming pin pair: serial data legend: i = input, o = output, p = power configuration register address fbs f80000 fgs f80004 foscsel f80006 fosc f80008 fwdt f8000a fpor f8000c ficd f8000e fds f80010 pic24fxxkaxxx device user memory no. of address limit (instruction words) no. of rows PIC24F08KA101 15fe (2.75k) 88 pic24f16ka101 2bfe (5.5k) 176 pic24f08ka102 15fe (2.75k) 88 pic24f16ka102 2bfe (5.5k) 176 pic24f04ka200 afe (1.375k) 44 pic24f04ka201 afe (1.375k) 44 note: an erase operation can be performed on one, two or four rows at a time, and a program operation can be performed on one row at a time. pic24fxxka1xx device data eeprom size in words no. of rows PIC24F08KA101 256 32 pic24f16ka101 256 32 pic24f08ka102 256 32 pic24f16ka102 256 32 note: an erase operation can be performed on one, four or eight words at a time and a program operation can be performed on one word at a time. pic24fxxkaxxx ds39919a-page 4 advance information ? 2008 microchip technology inc. figure 2-3: program memory map 000000h code memory configuration memory space (5632 x 24-bit) 800000h device id fefffeh ff0000h fffffeh reserved reserved 8007f0h programming executive 7ffe00h ff0002h ff0004h reserved (2 x 16-bit) note 1: the address boundaries for user flash code me mory are device dependent (see table 2-3). 2: pic24f04ka2xx devices have no data eeprom. user flash 8007eeh data eeprom (2) configuration registers f80010h f80000h diagnostic words 800800h 8007feh code memory afeh/15feh/2bfeh (1) (1016 x 24-bit) user memory space pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 5 3.0 device programming ? icsp the icsp method is a special programming protocol that allows reading and writing to the pic24fxxkaxxx device family memory. icsp is the most direct method used to program a device; however, enhanced icsp is faster. the icsp mode also reads the contents of the executive memory to determine if the programming executive is present. this is accomplished by applying control codes and instructions, serially to the device, using pgcx and pgdx pins. in icsp mode, the system clock is taken from the pgcx pin regardless of the device?s oscillator configuration bits. all of the instructions are shifted serially to an internal buffer, loaded into the instruction register (ir), and then executed. no program is fetched from the internal memory. instructions are fed in 24 bits at a time. pgdx is used to shift data in, and pgcx is used as both the serial shift clock and the cpu execution clock. 3.1 overview of the programming process figure 3-1 illustrates the high-level overview of the programming process. after entering the icsp mode, perform the following: 1. bulk erase the device. 2. program and verify the code memory. 3. program and verify the data eeprom memory. 4. program and verify the device configuration. 5. program the code-protect configuration bits if required. figure 3-1: high?level icsp? programming flow 3.2 icsp operation upon entry into icsp mode, the cpu is idle. an internal state machine governs the execution of the cpu. a 4-bit control code is clocked in, using pgcx and pgdx, and this control code is used to command the cpu (see table 3-1). the six control code is used to send instructions to the cpu for execution, and the regout control code is used to read data out of the device via the visi register. table 3-1: cpu control codes in icsp? mode note: during icsp operation, the operating frequency of pgcx should not exceed 10 mhz. 4-bit control code mnemonic description 0000b six shift in 24-bit instruction and execute. 0001b regout shift out the visi (0784h) register. 0010b-1111b n/a this is reserved. start perform bulk erase program memory verify program end enter icsp? mode program configuration bits verify configuration bits exit icsp mode program data eeprom memory verify data eeprom memory pic24fxxkaxxx ds39919a-page 6 advance information ? 2008 microchip technology inc. 3.2.1 six serial instruction execution the six control code allows execution of pic24fxxkaxxx family assembly instructions. when the six code is received, the cpu is suspended for 24 clock cycles as the instruction is then clocked into the internal buffer. once the instruction is shifted in, the state machine allows it to be executed over the next four pgc clock cycles. while the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see figure 3-2). coming out of reset, the first 4-bit control code is always forced to six, and a forced nop instruction is executed by the cpu. five additional pgcx clocks are needed on start-up; thereby resulting in a 9-bit six command, instead of the normal 4-bit six command. after the forced six is clocked in, the icsp operation resumes to normal. that is, the next 24 clock cycles load the first instruction word to the cpu. 3.2.1.1 differences between six instruction execution and normal instruction execution there are some differences between executing instructions using the six icsp command and normal device instruction execution. as a result, the code examples in this specification might not match those required to perform the same operations during normal device operation. the differences are: ? two-word instructions require 2 six operations to clock in all the necessary data. examples of two-word instructions are goto and call . ? two-cycle instructions require 2 six operations to complete. the first six operation shifts in the instruction and begins to execute it. a second six operation, which should shift in a nop to avoid losing data, allows the cpu clocks required to finish executing the instruction. examples of two-cycle instructions are table read and table write instructions. ? the cpu does not automatically stall to account for pipeline changes. a cpu stall occurs when an instruction modifies a register, which is used by the instruction immediately following the cpu stall for indirect addressing. during normal operation, the cpu forces a nop while the new data is read. to account for this, while using icsp, any indirect references to a recently modified register should be proceeded with a nop . for example, mov #0x0,w0 followed by mov [w0] , w1 must have a nop inserted in between. if a two-cycle instruction modifies a register, which is used indirectly, it requires two following nop s; one to execute the second half of the instruction and the other to stall the cpu to correct the pipeline. for example, tblwtl [w0++] , [w1] should be followed by 2 nop s. ? the device program counter (pc) continues to automatically increment during the icsp instruction execution, even though the flash memory is not being used. as a result, it is possible for the pc to be incremented so that it points to invalid memory locations. examples of invalid memory spaces are unimplemented flash addresses or the vector space (location 0x0 to 0x1ff). if the pc ever points to these locations, it causes the device to reset, possibly interrupting the icsp operation. to prevent this, instructions should be periodically executed to reset the pc to a safe space. the optimal method of achieving this is to perform a ? goto 0x200 ?. 3.2.2 regout serial instruction execution the regout control code allows for the data to be extracted from the device in the icsp mode. it is used to clock the contents of the visi register out of the device over the pgdx pin. after the regout control code is received, the cpu is held idle for 8 cycles. after this, an additional 16 cycles are required to clock the data out (see figure 3-3). the regout code is unique as the pgdx pin is an input when the control code is transmitted to the device. however, after the control code is processed, the pgdx pin becomes an output as the visi register is shifted out. note: to account for this forced nop , all example codes in this specification begin with a nop to ensure that no data is lost. note 1: after the contents of visi are shifted out, the pic24fxxkaxxx devices maintain pgdx as an output until the first rising edge of the next clock is received. 2: data changes on the falling edge and latches on the rising edge of pgcx. for all data transmissions, the least significant bit (lsb) is transmitted first. pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 7 figure 3-2: six serial execution figure 3-3: regout serial execution p4 23 123 2324 1 2 3 4 p1 pgcx p4a pgdx 24-bit instruction fetch execute pc ? 1, 16 0000 fetch six 456 78 1819202122 17 lsb x x x x x x x x x x x x x x msb pgdx = input p2 p3 p1b p1a 78 9 0000 00 0 only for program memory entry control code 4 5 execute 24-bit instruction, fetch next control code 00 1234 1278 pgcx p4 pgdx pgdx = input execute previous instruction, cpu held in idle shift out visi register<15:0> p5 pgdx = output 123 1234 p4a 11 13 15 16 14 12 no execution takes place, fetch next control code 0 0000 pgdx = input msb 1234 1 456 lsb 14 13 12 ... 11 10 0 fetch regout control code 0 pic24fxxkaxxx ds39919a-page 8 advance information ? 2008 microchip technology inc. 3.3 entering icsp mode 3.3.1 low-voltage icsp entry as illustrated in figure 3-4, the following processes are involved in entering icsp program/verify mode using mclr : 1. mclr is briefly driven high, then low. 2. a 32-bit key sequence is clocked into pgdx. 3. mclr is then driven high within a specified period of time and held. the programming voltage v ih is applied to mclr ; this is v dd in the case of pic24fxxkaxxx devices. there is no minimum time requirement for holding at v ih . after v ih is removed, an interval of at least p18 must elapse before presenting the key sequence on pgdx. the key sequence is a specific 32-bit pattern: ? 0100 1101 0100 0011 0100 1000 0101 0001 ? (more easily remembered as 4d434851h in hexadecimal). the device will enter program/verify mode only if the sequence is valid. the most significant bit (msb) of the most significant nibble must be shifted in first. once the key sequence is complete, v ih must be applied to mclr and held at that level for as long as the program/verify mode is to be maintained. an interval of at least p19 and p7 must elapse before presenting data on pgdx. signals appearing on pgcx before p7 has elapsed would not be interpreted as valid. 3.3.2 high-voltage icsp entry entering the icsp program/verify mode, using the v pp pin is the same as entering the mode using mclr . the only difference is the programming voltage applied to v pp is v ihh , and before presenting the key sequence on pgdx, an interval of at least p18 should elapse (see figure 3-5). once the key sequence is complete, an interval of at least p7 should elapse, and the voltage should remain at v ihh . the voltage, v ihh , must be held at that level for as long as the program/verify mode is to be main- tained. an interval of at least p7 must elapse before presenting the data on pgdx. signals appearing on pgdx before p7 has elapsed will not be interpreted as valid. upon a successful entry, the program memory can be accessed and programmed in serial fashion. while in icsp mode, all unused i/os are placed in a high-impedance state. figure 3-4: entering icsp? mode using low-voltage entry figure 3-5: entering icsp? mode using high-voltage entry mclr pgdx pgcx v dd p6 p14 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434851h p1a p1b p18 p19 0100 0 0 p7 v ih v ih 1 0 1 v pp pgdx pgcx v dd p6 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434851h p1a p1b p18 0100 0 0 1 0 1 v ihh v ih p7 pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 9 3.4 flash memory programming in icsp mode 3.4.1 programming operations the nvmcon register controls the flash memory write and erase operations. to program the device, set the nvmcon register to select the type of erase operation (see table 3-2) or write operation (see table 3-3). set the wr control bit (nvmcon<15>) to initiate the program. in icsp mode, all programming operations are self-timed. there is an internal delay between setting and automatic clearing of the wr control bit when the programming operation is complete. refer to section 7.0 ?ac/dc characteristics and timing requirements? for information on the delays associated with various programming operations. table 3-3: nvmcon values for write operations 3.4.2 starting and stopping a programming cycle the wr bit (nvmcon<15>) is used to start an erase or write cycle. initiate the programming cycle by setting the wr bit. all erase and write cycles are self-timed. the wr bit should be polled to determine if the erase or write cycle is completed. start a programming cycle as follows: bset nvmcon, #wr 3.5 erasing program memory to erase the program memory (all of code memory, data memory and configuration bits, including the code-protect bits), set the nvmcon to 4064h and then execute the programming cycle. figure 3-6 illustrates the icsp programming process for bulk erase. this process includes the icsp command code, which must be transmitted (for each instruction), lsb first, using the pgcx and pgdx pins (see figure 3-2). table 3-4 provides the steps for executing serial instruction for the bulk erase mode. figure 3-6: bulk erase flow table 3-2: nvmcon values for erase operations nvmcon value erase operation 4064h erase the code memory and configuration registers (does not erase programming executive code and device id registers). 404ch erase the general segment and configuration bits associated with it. 4068h erase the boot segment and configuration bits associated with it. 405ah (1) erase four rows of code memory. 4059h (1) erase two rows of code memory. 4058h (1) erase a row of code memory. 4050h erase the entire data eeprom memory and configuration bits associated with it. 405ah (1) erase eight words of data eeprom memory. 4059h (1) erase four words of data eeprom memory. 4058h (1) erase one word of data eeprom memory. 4054h erase all the configuration registers (except the code-protect fuses). 4058h (1) erase configuration registers except fbs and fgs. note 1: the destination address decides the region (code memory, data eeprom memory or configuration register) of the erased rows/words. nvmcon value write operation 4004h (1) write one configuration register. 4004h (1) program one row (32 instruction words) of code memory or executive memory. 4004h (1) program one word of data eeprom memory. note 1: the destination address decides the region (code memory, data eeprom memory or configuration register) of the erased rows/words. note: program memory must be erased before writing any data to program memory. end set the wr bit to initiate erase write 4064h to nvmcon sfr delay p11 + p10 time start pic24fxxkaxxx ds39919a-page 10 advance information ? 2008 microchip technology inc. table 3-4: serial instruction execution for chip erase 3.6 writing code memory the procedure for writing code memory is the same as writing the configuration registers. the difference is that the 32 instruction words are programmed one at a time. to facilitate this operation, working registers, w0:w5, are used as temporary holding registers for the data to be programmed. figure 3-8 illustrates the code memory writing flow. table 3-5 provides the icsp programming details, including the serial pattern with the icsp command code, which must be transmitted lsb first, using the pgcx and pgdx pins (see figure 3-2). in step 1 of table 3-5, the reset vector is exited; in step 2, the nvmcon register is initialized for programming a full row of code memory, and in step 3, the 24-bit starting destination address for programming is loaded into the tblpag register and w7 register. the upper byte of the starting destination address is stored in tblpag and the lower 16 bits of the destination address are stored in w7. to minimize the programming time, a packed instruction format is used (see figure 3-7). in step 4 of table 3-5, four packed instruction words are stored in working registers, w0:w5, using the mov instruction; the read pointer, w6, is initialized. figure 3-7 illustrates the contents of w0:w5 holding the packed instruction word data. in step 5, eight tblwt instructions are used to copy the data from w0:w5 to the write latches of the code memory. since code memory is programmed 32 instruction words at a time, steps 3 to 5 are repeated eight times to load all the write latches (see step 6). after the write latches are loaded, initiate programming by writing to the nvmcon register in steps 7 and 8. in step 9, the internal pc is reset to 200h. this is a precautionary measure to prevent the pc from incrementing to unimplemented memory when large devices are being programmed. finally, in step 10, repeat steps 3 through 9 until all of the code memory is programmed. command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: set the nvmcon to erase the entire program memory. 0000 0000 24064a 883b0a mov #0x4064, w10 mov w10, nvmcon step 3: set the tblpag and perform dummy table write to select the erased memory. 0000 0000 0000 0000 0000 0000 200000 880190 200000 bb0800 000000 000000 mov # pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 11 figure 3-7: pack ed instruction words in w0:w5 15 8 7 0 w0 lsw0 w1 msb1 msb0 w2 lsw1 w3 lsw2 w4 msb3 msb2 w5 lsw3 table 3-5: serial instruction exec ution for writing code memory command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: set the nvmcon to program 32 instruction words. 0000 0000 24004a 883b0a mov #0x4004, w10 mov w10, nvmcon step 3: initialize the write pointer (w7) for tblwt instruction. 0000 0000 0000 200xx0 880190 2xxxx7 mov # pic24fxxkaxxx ds39919a-page 12 advance information ? 2008 microchip technology inc. step 5: set the read pointer (w6) and load the (next set of) write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 eb0300 000000 bb0bb6 000000 000000 bbdbb6 000000 000000 bbebb6 000000 000000 bb1bb6 000000 000000 bb0bb6 000000 000000 bbdbb6 000000 000000 bbebb6 000000 000000 bb1bb6 000000 000000 clr w6 nop tblwtl [w6++], [w7] nop nop tblwth.b [w6++], [w7++] nop nop tblwth.b [w6++], [++w7] nop nop tblwtl [w6++], [w7++] nop nop tblwtl [w6++], [w7] nop nop tblwth.b [w6++], [w7++] nop nop tblwth.b [w6++], [++w7] nop nop tblwtl [w6++], [w7++] nop nop step 6: repeat steps 3 though 5, eight times, to load the write latches for 32 instructions. step 7: initiate the write cycle. 0000 0000 0000 a8e761 000000 000000 bset nvmcon, #wr nop nop step 8: repeat this step to poll the wr bit (bit 15 of nvmcon) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803b02 883c22 000000 pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 13 figure 3-8: program code memory flow start write sequence all locations done? no end start yes load 2 bytes to write buffer at pic24fxxkaxxx ds39919a-page 14 advance information ? 2008 microchip technology inc. 3.7 writing data eeprom figure 3-9 illustrates the flow of programming the data eeprom memory. the procedure is the same as writing code memory. the only difference is that only one word is programmed in each operation. when writing data eeprom, one word is programmed during each operation. working register, w0, is used as a temporary holding register for the data to be programmed. table 3-6 provides the icsp programming details for writing data eeprom. figure 3-9: program dat a eeprom memory flow note: the tblpag register is hard-coded to 0x7f (the upper byte address of all locations of data eeprom). start write sequence all locations done? no end start yes load 2 bytes to write buffer at pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 15 table 3-6: instruction execut ion for writing data eeprom command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2 : set the nvmcon to program 1 data word. 0000 0000 24004a 883b0a mov #0x4004, w10 mov w10, nvmcon step 3: initialize the write pointer (w7) for tblwt instruction. 0000 0000 0000 2007f0 880190 2fexx7 mov #0x7f, w0 mov w0, tblpag mov # pic24fxxkaxxx ds39919a-page 16 advance information ? 2008 microchip technology inc. 3.8 writing configuration registers the procedure for writing the configuration registers is the same as for writing code memory. the only differ- ence is that, only one word is programmed in each operation. when writing configuration registers, one word is programmed during each operation, only work- ing register, w0, is used as a temporary holding register for the data to be programmed. table 3-7 provides the default values of the configuration registers. table 3-7 provides the icsp programming details for programming the configuration registers, including the serial pattern with the icsp command code, which must be transmitted lsb first using the pgcx and pgdx pins (see figure 3-2). in step 1 of table 3-8, the reset vector is exited. in step 2, the nvmcon register is initialized for programming code memory. in step 3, the 24-bit starting destination address for programming is loaded into the tblpag register and w7 register. table 3-7: default values for configuration register serial instruction note: the tblpag register is hard-coded to 0xf8 (the upper byte address of all locations of the configuration registers). note: the tblpag register must be loaded with f8h. configuration registers value fbs (3) 0fh fgs 03h foscsel 87h fosc ffh fwdt dfh fpor (1) fbh ficd (2,3) c3h fds (4) ffh note 1: the i2c2sel bit (fpor<4>) is not implemented on pic24fxxkax01 and pic24fxxkax00 devices and should be programmed as ? 1 ?. 2: the ficd<6> bit is a reserved bit and should be programmed as ? 1 ?. 3: the configuration registers, fbs and ficd, are reserved locations on pic24f04ka2xx devices, and should be programmed with the default value given above. 4: the rtcsosc bit (fds<5>) is not implemented on pic24f04ka2xx devices, and should be programmed as ? 1 ?. pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 17 table 3-8: serial instruction executio n for writing configuration registers command (binary) data (hex) command (binary) step 1: exit the reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize the write pointer (w7) for the tblwt instruction. 0000 200007 mov #0x0000, w7 step 3: set the nvmcon register to program configuration registers. 0000 0000 24004a 883b0a mov #0x4004, w10 mov w10, nvmcon step 4: initialize the tblpag register. 0000 0000 200f80 880190 mov #0xf8, w6 mov w0, tblpag step 5: load the configuration register data to w6. 0000 2xxxx6 mov # pic24fxxkaxxx ds39919a-page 18 advance information ? 2008 microchip technology inc. 3.9 reading code memory to read the code memory, execute a series of tblrd instructions and clock out the data using the regout command. table 3-9 provides the icsp programming details for reading code memory. in step 1, the reset vector is exited. in step 2, the 24-bit starting source address for reading is loaded into the tblpag register and the w6 register. the upper byte of the starting source address is stored in tblpag, and the lower 16 bits of the source address are stored in w6. to minimize the reading time, the packed instruction word format, which was used for writing, is also used for reading (see figure 3-7). in step 3, the write pointer, w7, is initialized. in step 4, two instruction words are read from code memory, and clocked out of the device through the visi register, using the regout command. step 4 is repeated until the required amount of code memory is read. table 3-9: serial instruction execution for reading code memory command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize tblpag and the read pointer (w6) for tblrd instruction. 0000 0000 0000 200xx0 880190 2xxxx6 mov # pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 19 3.10 reading data eeprom memory the procedure for reading data eeprom memory is the same as reading the code memory. the only differ- ence is that the 16-bit data words are read instead of the 24-bit words. table 3-10 provides the icsp programming details for reading data memory. table 3-10: serial instruction execution for reading data eeprom memory note: the tblpag register is hard-coded to 0x7f (the upper byte address of all locations of data memory). command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize tblpag and the read pointer (w6) for tblrd instruction. 0000 0000 0000 2007f0 880190 2fexx6h mov #0x7f, w0 mov w0, tblpag mov # pic24fxxkaxxx ds39919a-page 20 advance information ? 2008 microchip technology inc. 3.11 reading configuration memory the procedure for reading a configuration register is the same as reading the code memory. the only difference is that the 16-bit data words are read (with the upper byte read being all ? 0 ?s) instead of the 24-bit words. there are eight configuration registers and they are read one register at a time. table 3-11 provides the icsp programming details for reading all of the configuration registers. note: the tblpag register should be hard-coded to 0xf8 (the upper byte address of the configuration register) and the read pointer, w6, is initialized to 0x00h. table 3-11: serial instruction execution for reading all the configuration registers command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize tblpag, the read pointer (w6) and the write pointer (w7) for tblrd instruction. 0000 0000 0000 0000 0000 200f80 880190 200007 207847 000000 mov #0xf8, w0 mov w0, tblpag mov #0x0000,w6 mov #visi, w7 nop step 3: read the configuration register and write it to the visi register (located at 784h), and clock out the visi register using the regout command. 0000 0000 0000 0001 ba0bb6 000000 000000 pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 21 3.12 verifying code memory, data eeprom memory and configuration registers to verify the code memory, read the code memory space and compare it with the copy held in the programmer?s buffer. to verify the data eeprom and configuration registers, follow the similar procedure. figure 3-10 illustrates the verify process flowchart. memory reads occur 1 byte at a time, hence 2 bytes must be read to compare with the word in the programmer?s buffer. refer to section 3.9 ?reading code memory? for implementation details of reading code memory. on the same lines, the data eeprom and configuration registers can be verified. figure 3-10: verify code memory flow 3.13 reading the application id word the application id word is stored in address 8005beh in the executive code memory. to read this memory location, use the six control code to move this program memory location to the visi register. then, the regout control code must be used to clock the contents of the visi register out of the device. table 3-12 provides the corresponding control and instruction codes that must be serially transmitted to the device to perform this operation. after the programmer has clocked out the application id word, it must be inspected. if the application id has the value, bbh, the programming executive resides in the memory and the device can be programmed using the mechanism described in section 4.0 ?device programming ? enhanced icsp? . however, if the application id has any other value, the programming executive does not reside in the memory; it must be loaded to memory before the device can be programmed. section 5.4 ?programming the programming executive to memory? describes the procedure for loading the programming executive to memory. 3.14 exiting icsp mode exit the program/verify mode by removing v ih from mclr /v pp as illustrated in figure 3-11. the only requirement to exit is that an interval of p16 should elapse between the last clock and program signals on pgcx and pgdx before removing v ih . figure 3-11: exiting icsp? mode note: code memory should be verified immediately after writing if code protection is enabled. since configuration registers include the device code protection bit, the device will not be readable or verifiable if a device reset occurs after the code-protect bits are set (value = 0 ). read low byte read high byte does word = expect data? all code memory verified? no yes no set tblptr = 0 start yes end with post-increment with post-increment failure report error mclr /v pp p16 pgdx pgd = input pgcx v dd v ih /v ihh v ih p17 pic24fxxkaxxx ds39919a-page 22 advance information ? 2008 microchip technology inc. table 3-12: serial instruction execution for reading the application id word command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize tblpag and the read pointer (w0) for tblrd instruction. 0000 0000 0000 0000 0000 0000 0000 0000 200800 880190 205be0 207841 000000 ba0890 000000 000000 mov #0x80, w0 mov w0, tblpag mov #0x5be, w0 mov #visi, w1 nop tblrdl [w0], [w1] nop nop step 3: output the visi register using the regout command. 0001 0000 pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 23 4.0 device programming ? enhanced icsp this section describes the programming of the device through enhanced icsp and the programming executive. the programming executive resides in the executive memory (separate from user memory space), and is executed when enhanced icsp programming mode is entered. the programming executive provides the mechanism for the programmer (host device) to program and verify the pic24fxxkaxxx devices using a simple command set and communication protocol. the basic functions provided by the programming executive are: ? read memory ? program memory ? blank check ? read executive firmware revision the programming executive performs the low-level tasks required for erasing, programming and verifying a device. this allows the programmer to program the device by issuing the appropriate commands and data. table 4-1 provides these commands. for detailed descriptions of each command, see section 5.2 ?programming executive commands? . table 4-1: command set summary the programming executive uses the device?s data ram for variable storage and program execution. after the programming executive is run, no assumptions should be made about the contents of the data ram. 4.1 overview of the programming process figure 4-1 illustrates the high-level overview of the programming process. perform the following steps: 1. enter icsp mode. 2. erase the device. 3. verify the programming executive. 4. exit icsp mode. 5. enter enhanced icsp mode. 6. program the code memory. 7. verify the code memory. 8. program the configuration registers. 9. verify the configuration registers. steps 7 and 9 ensure that the programming was successful. after the programming executive is verified in memory (or loaded if not present), the pic24fxxkaxxx family can be programmed using the command set provided in table 4-1. figure 4-1: high-level enhanced icsp? programming flow command description scheck sanity check. readc read device id registers. readd read data eeprom memory. readp read code register. progc write user id. progd program and verify one word of data eeprom memory. progp program and verify one row of code memory or one configuration register. qblank query if the code memory is blank. qver query the software version. start end perform chip erase program and verify enter icsp? mode program and verify exit enhanced icsp mode program and verify code memory data eeprom memory configuration bits enter enhanced icsp mode exit icsp mode pic24fxxkaxxx ds39919a-page 24 advance information ? 2008 microchip technology inc. 4.2 confirming the presence of the programming executive before beginning programming, confirm if the programming executive is stored in the executive memory and perform the following: 1. enter in-circuit serial programming mode (icsp). 2. read the unique application id word stored in the executive memory. figure 4-2 illustrates this procedure. if the programming executive is resident, the application id word is bbh, which means programming can resume as normal. however, if the application id word is not bbh, the programming executive must be programmed to executive code memory using the method described in section 5.4 ?programming the programming executive to memory? . section 3.0 ?device programming ? icsp? describes the icsp programming method. section 3.13 ?reading the application id word? describes the procedure for reading the application id word in icsp mode. figure 4-2: confir ming presence of programming executive 4.3 entering enhanced icsp mode 4.3.1 low-voltage entry perform the following steps to enter enhanced icsp program/verify mode using mclr : 1. briefly drive the mclr pin high, and then low. 2. clock a 32-bit key sequence into pgdx. 3. drive the mclr high within a specified period and continue to hold high. figure 4-3 illustrates this procedure. the programming voltage applied to mclr is v ih , which is essentially v dd in the case of pic24fxxkaxxx devices. there is no minimum time requirement for holding at v ih . after v ih is removed, an interval of at least p18 must elapse before presenting the key sequence on pgdx. the key sequence is a specific 32-bit pattern: ? 0100 1101 0100 0011 0100 1000 0101 0000 ? (more easily remembered as 4d434850h in hexadecimal format). the device will enter program/verify mode only if the key sequence is valid. the msb of the most significant nibble must be shifted in first. once the key sequence is complete, v ih must be applied to mclr and held at that level for as long as the program/verify mode is to be maintained. an interval of at least p19 and p7 must elapse before presenting data on pgdx. signals appearing on pgdx before p7 has elapsed will not be interpreted as valid. 4.3.2 high-voltage entry the procedure for entering enhanced icsp program/verify mode using the v pp pin is the same as entering the mode using mclr . the only differences are that the programming voltage applied to v pp is v ihh , and before presenting the key sequence on pgdx, an interval of at least p18 should elapse. figure 4-4 illustrates this procedure. once the key sequence is complete, an interval of at least p19 should elapse and the v ihh should be reduced to v ih . the voltage, v ih , must be applied to v pp and held at that level for as long as the program/verify mode is to be maintained. an interval of at least p19 and p7 should elapse before presenting data on pgdx. signals appearing on pgdx before p7 has elapsed will not be interpreted as valid. on successful entry, the program memory can be accessed and programmed in serial fashion. while in the program/verify mode, all unused i/os are placed in the high-impedance state. is start enter icsp? mode application id bbh? resident in memory yes no prog. executive is application id read the be programmed prog. executive must from address 805beh finish pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 25 figure 4-3: entering enhanced icsp? mode using low-voltage entry figure 4-4: entering enhanced icsp? mode using high-voltage entry 4.4 blank check the term ?blank check? implies verifying if the device has been successfully erased and has no programmed memory locations. a blank or erased memory location is always read as ? 1 ?. the device id registers (ff0002h:ff0000h) can be ignored by the blank check as this region stores device information that cannot be erased. the device configuration registers are also ignored by the blank check. additionally, all unimplemented memory space should be ignored by the blank check. the qblank command is used for the blank check. it determines if the code memory is erased by testing these memory regions. a ?blank? or ?not blank? response is returned. if it is determined that the device is not blank, it must be erased before attempting to program the device. 4.5 code memory programming 4.5.1 programming methodology code memory is programmed with the progp command. progp programs one row of code memory, starting from the memory address specified in the command. the number of progp commands required to program a device depends on the number of write blocks that must be programmed in the device. figure 4-5 illustrates an example flowchart for programming code memory. in this example, all 5.5k instruction words of a pic24fxxkaxxx device are programmed. ? first, the number of commands to send (titled ?remainingcmds? in the flowchart) is set to 176, and the destination address (called ?baseaddress?) is set to ? 0 ?. ? next, one write block in the device is programmed with a progp command. each progp command contains data for one row of code memory of the pic24fxxkaxxx device. ? after the first command is processed successfully, ?remainingcmds? is decremented by 1 and compared with 0. since there are more progp commands to be sent, ?baseaddress? is incremented by 40h to point to the next row of memory. on the second progp command, the second row is programmed. this process is repeated until the entire device is programmed. special handling should not be performed when a panel boundary is crossed. mclr pgdx pgcx v dd p6 p14 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434850h p1a p1b p18 p19 01001 0000 p7 v ih v ih v pp pgdx pgcx v dd p6 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434850h p1a p1b p18 01001 0000 v ihh p7 pic24fxxkaxxx ds39919a-page 26 advance information ? 2008 microchip technology inc. 4.5.2 programming verification after the code memory is programmed, the contents of the memory can be verified to ensure that the programming is successful. verification requires the code memory to be read back and compared with the copy held in the programmer?s buffer. the readp command can be used to read back all of the programmed code memory. alternatively, you can have the programmer perform the verification after the entire device is programmed using a checksum computation. figure 4-5: flowchart for programming code memory 4.6 data eeprom programming 4.6.1 programming methodology the programming executive uses the progd command to program the data eeprom. figure 4.7 illustrates this process. ? first, the number of words to program (remainingwords) is based on the device size and the destination address (destaddress) is set to 0. in this example, 256 words of data eeprom will be programmed. ? the first progd command programs the first word of data eeprom. ? once the command completes successfully, ?remainingwords? is decremented by 1 and compared with 0. ? since there are 255 more words to program, ?baseaddress? is incremented by 02h to point to the next word of data eeprom. ? this process is then repeated until all 256 words of data eeprom are programmed. 4.6.2 programming verification once the data eeprom is programmed, the contents of the memory can be verified to ensure if the programming was successful. verification requires the data eeprom to be read back and compared with the copy held in the programmer?s buffer. the readd command reads back the programmed data eeprom. alternatively, the programmer can perform the verification once the entire device is programmed using a checksum computation, as described in section 6.1.1 ?checksum computation?. is progp response pass? are remainingcmds ? 0 ?? baseaddress = 00h remainingcmds = 176 remainingcmds = remainingcmds ? 1 baseaddress = baseaddress + 40h no no ye s yes start failure report error send progp command to program baseaddress end pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 27 figure 4-6: flowchart for programming data eeprom 4.7 configuration bits programming the pic24fxxkaxxx family ha s eight configuration registers . the bits of these registers can be set or cleared to select various device configurations. there are three types of configuration bits: ? system operation bits these bits determine the power-on settings for system-level components, such as the oscillator and watchdog timer. ? code-protect bits these bits prevent program memory from being read and written. ? device id bits these are read-only bits, which are located from ff0000 to ff0003, and are unique to every device. table 4-2 provides the configuration registers. 4.7.1 programming methodology configuration bits may be programmed, a single byte at a time, using the progp command. this command specifies the configuration data and configuration register address. when configuration bits are programmed, any unimplemented or reserved bits must be programmed with a ? 1 ?. eight progp commands are required to program the configuration bits. figure 4-7 illustrates the flowchart for configuration bit programming. 4.7.2 programming verification after the configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. verification requires the configuration bits to be read back and compared against the copy held in the programmer?s buffer. the readp command reads back the programmed configuration bits and verifies that the programming was successful. is progd response pass? are remainingwords ? 0 ?? remainingwords = 256 (100h) baseaddress = 0 remainingwords = remainingwords ? 1 baseaddress = baseaddress + 02h no no yes yes start failure report error send progd command to program baseaddress finish note: if the general segment code-protect bit (gcp) is programmed to ? 0 ?, code memory is code-protected and cannot be read. code memory must be verified before enabling code protection. see section 4.7.3 ?code-protect configuration bits? for more information on code-protect configuration bits. pic24fxxkaxxx ds39919a-page 28 advance information ? 2008 microchip technology inc. 4.7.3 code-protect configuration bits the fbs and fgs configuration registers are special configuration registers which control the code protection for the boot segment and general segment, respectively. for each segment, two forms of code protection are provided. one form prevents code memory from being written (write protection), while the other prevents it from being read (read protection). the bwrp and gwrp bits control write protection and the bss0 and gss0 bits control read protection. when write protection is enabled, any programming operation to code memory will fail. when read protection is enabled, any read from code memory will cause a 00h to be read, regardless of the actual contents of code memory. since the programming executive always verifies what it programs, attempting to program code memory with read protection enabled also results in failure. it is imperative that all code protection bits should be ? 1 ? while the device is being programmed, and verified. only after the device is programmed and verified should any of the above bits be programmed to ? 0 ? (see section 4.7 ?configuration bits programming? ). note: all bits in the fbs and fgs configuration registers can only be programmed to a value of ? 0 ? . bulk erasing the chip is the only way to reprogram code-protect bits from on (? 0 ?) to off (? 1 ?). table 4-2: pic24fxxkaxxx family configuration bits description bit field register description boren<1:0> fpor<1:0> brown-out reset enable bits 11 = brown-out reset enabled in hardware; sboren bit disabled 10 = brown-out reset enabled only while device is active and disabled in sleep; sboren bit disabled 01 = brown-out reset controlled with the sboren bit setting 00 = brown-out reset disabled in hardware; sboren bit disabled borv<1:0> fpor<6:5> brown-out reset voltage bits 11 = v bor set to 1.8v min 10 = v bor set to 2.0v min 01 = v bor set to 2.7v min 00 = downside protection on por enabled ? ?zero-power? selected bss0 fbs<3> boot segment program flash code protection bit 1 = no protection 0 = standard security enabled bsz<1:0> fbs<2:1> boot segment program flash size selection bits 11 = no boot program flash segment 10 = boot program flash segment starts at 200h, ends at 000afeh 01 = boot program flash segment starts at 200h, ends at 0015feh 00 = reserved bwrp fbs<0> boot segment program flash write protection bit 1 = boot segment may be written 0 = boot segment is write-protected debug ficd<7> background debugger enable bit 1 = background debugger disabled 0 = background debugger functions enabled dswdten fds<7> deep sleep watchdog timer enable bit 1 = dswdt enabled 0 = dswdt disabled dswcksel fds<4> dswdt reference clock select bit 1 = dswdt uses lprc as reference clock 0 = dswdt uses sosc as reference clock note 1: applies only to the 28-pin device. 2: the mclre fuse can only be changed when using the v pp -based test mode entry. this prevents a user from accidentally locking out the device from low-voltage test entry. pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 29 dswdtps<3:0> fds<3:0> deep sleep watchdog timer postscale select bits the dswdt prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) dszpbor fds<6> deep sleep zero-power bor enable bit 1 = zero-power bor enabled in deep sleep 0 = zero-power bor disabled in deep sleep (does not affect operation in non deep sleep modes) fcksm<1:0> fosc<7:6> clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled fnosc<2:0> foscsel<2:0> oscillator selection bits 000 = fast rc oscillator (frc) 001 = fast rc oscillator with divide-by-n with pll module (frcdiv+pll) 010 = primary oscillator (xt, hs, ec) 011 = primary oscillator with pll module (hs+pll, ec+pll) 100 = secondary oscillator (sosc) 101 = low-power rc oscillator (lprc) 110 = reserved; do not use 111 = fast rc oscillator with divide-by-n (frcdiv) fwdten fwdt<7> watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) gss0 fgs<1> general segment code flash code protection bit 1 = no protection 0 = standard security enabled gwrp fgs<0> general segment code flash write protection bit 1 = general segment may be written 0 = general segment is write-protected ics<1:0> ficd<1:0> icd pin placement select bit 11 = icd emuc/emud pins are shared with pgec1/pged1 10 = icd emuc/emud pins are shared with pgec2/pged2 01 = icd emuc/emud pins are shared with pgec3/pged3 00 = reserved; do not use table 4-2: pic24fxxkaxxx family config uration bits description (continued) bit field register description note 1: applies only to the 28-pin device. 2: the mclre fuse can only be changed when using the v pp -based test mode entry. this prevents a user from accidentally locking out the device from low-voltage test entry. pic24fxxkaxxx ds39919a-page 30 advance information ? 2008 microchip technology inc. ieso foscsel<7> internal external switchover bit 1 = internal external switchover mode enabled (two-speed start-up enabled) 0 = internal external switchover mode disabled (two-speed start-up disabled) i2c1sel (1) fpor<4> alternate i2c1 pin mapping bit (1) 0 = alternate location for scl1/sda1 pins 1 = default location for scl1/sda1 pins mclre (2) fpor<7> mclr pin enable bit (2) 1 = mclr pin enabled; ra5 input pin disabled 0 = ra5 input pin enabled; mclr disabled osciofnc fosc<2> clko enable configuration bit 1 = clko output signal active on the osco pin; primary oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmd<1:0> = 11 or 00 ) 0 = clko output disabled poscmd<1:0> fosc<1:0> primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs oscillator mode selected (4 mhz-25 mhz) 01 = xt oscillator mode selected (100 khz-4 mhz) 00 = external clock mode selected poscfreq<1:0> fosc<4:3> primary oscillator frequency range configuration bits 11 = primary oscillator/external clock input frequency greater than 8 mhz 10 = primary oscillator/external clock input frequency between 100 khz and 8 mhz 01 = primary oscillator/external clock input frequency less than 100 khz 00 = reserved, do not use pwrten fpor<3> power-up timer enable bit 0 = pwrt disabled 1 = pwrt enabled rtccksel fds<5> rtcc reference clock select bit 1 = rtcc uses sosc as reference clock 0 = rtcc uses lprc as reference clock soscsel fosc<5> secondary oscillator select bit 1 = secondary oscillator configured for high-power operation 0 = secondary oscillator configured for low-power operation wdtpre fwdt<4> wdt prescaler 1 = wdt prescaler ratio of 1:128 0 = wdt prescaler ratio of 1:32 wdtpost<3:0> fwdt<3:0> watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 ? ? ? 0001 = 1:2 0000 = 1:1 windis fwdt<6> windowed watchdog timer disable bit 1 = standard wdt selected; windowed wdt disabled 0 = windowed wdt enabled table 4-2: pic24fxxkaxxx family config uration bits description (continued) bit field register description note 1: applies only to the 28-pin device. 2: the mclre fuse can only be changed when using the v pp -based test mode entry. this prevents a user from accidentally locking out the device from low-voltage test entry. pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 31 figure 4-7: conf iguration bit pr ogramming flow 4.8 exiting the enhanced icsp mode to exit the program/verify mode, remove v ih from mclr /v pp , as illustrated in figure 4-8. for exiting, an interval p16 should elapse between the last clock and program signals on pgcx and pgdx before removing v ih . figure 4-8: exiting enhanced icsp? mode send progp command configaddress = f80000h is progp response pass? no yes no failure report error start end yes is configaddress f80010h? configaddress = configaddress + 2 mclr /v pp p16 pgdx pgdx = input pgcx v dd v ih /v ihh v ih p17 pic24fxxkaxxx ds39919a-page 32 advance information ? 2008 microchip technology inc. 5.0 the programming executive this section describes the programming executive communication, programming executive commands, programming responses, programming the programming executive to memory and programming verification. 5.1 programming executive communication the programmer and the programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave. communication is initiated by the programmer in the form of a command. only one command at a time can be sent to the programming ex ecutive. the programming executive, in turn, only sends one response to the programmer after receiving and processing a command. the programming executive command set is described in section 5.2 ?programming executive commands? . the response set is described in section 5.3 ?programming executive responses? . 5.1.1 communication interface and protocol the enhanced icsp interface is a two-wire spi, implemented using the pgcx and pgdx pins. the pgcx pin is used as a clock input pin; the programmer should provide the clock source. the pgdx pin is used to send the command data to, and receive response data from, the programming executive. data transmits to the device should change on the rising edge and hold on the falling edge of pgcx. data receives from the device change on the falling edge and holds on the rising edge of pgcx. the data transmissions are sent to the msb first using 16-bit mode (see figure 5-1 and figure 5-2). figure 5-1: programming executive serial timing for data received from device as a 2-wire spi is used and data transmissions are half-duplex, a simple protocol is used to control the direction of pgdx. when the programmer completes a command transmission, it releases the pgdx line and allows the programming executive to drive this line high. the programming executive keeps the pgdx line high to indicate that it is processing the command. after the programming executive has processed the command, it brings pgdx low for 15 sec to indicate to the programmer that the response is available to be clocked out. the programmer can begin to clock out the response 23 sec after pgdx is brought low, and it must provide the necessary amount of clock pulses to receive the entire response from the programming executive. after the entire response is clocked out, the programmer should terminate the clock on pgcx until it is time to send another command to the programming executive; figure 5.2 displays this protocol. 5.1.2 spi rate in enhanced icsp mode, the pic24fxxkaxxx family devices operate from the internal fast rc oscillator, which has a nominal frequency of 8 mhz. this oscillator frequency yields an effective system clock frequency of 4 mhz. to ensure that the programmer does not clock too fast, it is recommended that a 4 mhz clock be provided by the programmer. figure 5-2: programming executive serial timing for data transmitted to device pgcx pgdx 123 11 13 15 16 14 12 lsb 14 13 12 11 45 6 msb 1 2 3 ... 4 5 p2 p3 p1 p1b p1a pgcx pgdx 123 11 13 15 16 14 12 lsb 14 13 12 11 45 6 msb 1 2 3 ... 4 5 p2 p3 p1 p1b p1a pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 33 5.1.3 time-outs the programming executive does not use the watch- dog timer or time-out for transmitting responses to the programmer. if the programmer does not follow the flow control mechanism using pgcx, as described in section 5.1.1 ?communication interface and proto- col? , it is possible that the programming executive will behave unexpectedly while trying to send a response to the programmer. since the programming executive does not have a time-out, it is imperative that the pro- grammer correctly follow the described communication protocol. as a safety measure, the programmer should use the command time-outs identified and listed in table 5-1. if the command time-out expires, the programmer should reset the programming executive and start programming the device again. figure 5-3: programming executive ? programmer communication protocol 5.2 programming executive commands the programming executive command set is listed in table 5-1. this table contains the opcode, mnemonic, length, time-out and description for each command. section 5.2.4 ?command descriptions? provides functional details on each command. 5.2.1 command format the programming executive commands have a general format consisting of a 16-bit header and any required data for the command (see figure 5-4). the 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. figure 5-4: command format the command opcode must match one of those in the command set. any command that is received that does not match the list in table 5-1 returns a ?nack? response (see section 5.3.1.1 ?opcode field? ). the command length is represented in 16-bit words as the spi operates in 16-bit mode. the programming executive uses the command length field to determine the number of words to read from the spi port. if the value of this field is incorrect, the command will not be properly received by the programming executive. 1 2 15 16 12 1516 pgcx pgdx pgcx = input pgcx = input (idle) host transmits last command word pgdx = input pgdx = output p8 1 2 15 16 msb x x x lsb msb x x x lsb msb x x x lsb 1 0 p20 pgcx = input pgdx = output p9 programming executive processes command host clocks out response p21 15 12 11 0 opcode length command data first word (if required) ? ? command data last word (if required) pic24fxxkaxxx ds39919a-page 34 advance information ? 2008 microchip technology inc. 5.2.2 packed data format when 24-bit instruction words are transferred across the 16-bit spi interface, they are packed to conserve space using the format illustrated in figure 5-5. this format minimizes the traffic over the spi and provides the programming executive the data that is properly aligned for performing table write operations. figure 5-5: pack ed instruction word format 5.2.3 programming executive error handling the programming executive will ?nack? all unsupported commands. additionally, due to the memory constraints of the programming executive, no checking is performed on the data contained in the programmer command. it is the responsibility of the programmer to command the programming executive with valid command arguments; otherwise, the programming operation might fail. section 5.3.1.3 ?qe_code field? provides additional information on error handling. note: when the number of instruction words transferred is odd, msb2 is zero and lsw2 cannot be transmitted. 15 8 7 0 lsw1 msb2 msb1 lsw2 lswx: least significant 16 bits of instruction word msbx: most significant bits of instruction word table 5-1: programming executive command set opcode mnemonic length (16-bit words) time-out description 0h scheck 1 1 msec sanity check. 1h readc 3 1 msec read up to (256) 8-bit words starting from the specified device id register. 2h readp 4 1 msec/row read up to 32k instruction words of code memory starting from the specified address. (1) 3h reserved n/a n/a this command is reserved; it returns a nack. 4h progc 4 5 msec write an 8-bit word to the specified device id registers. 5h progp 99 5 msec program up to 32 instructions (one row) of code memory at the specified address and then verify. (1) 6h reserved n/a n/a this command is reserved; it returns a nack. 7h reserved n/a n/a this command is reserved; it returns a nack. 8h reserved n/a n/a this command is reserved; it returns a nack. 9h reserved n/a n/a this command is reserved; it returns a nack. ah qblank 3 tbd query if the code memory is blank. (1) bh qver 1 1 msec query the programming executive software version. ch reserved n/a n/a this command is reserved; it returns a nack. dh reserved n/a n/a this command is reserved. it returns a nack. eh readd 4 1 msec/word read up to (256) 16-bit words starting from the specified address. fh progd 19 5 msec program one word of data eeprom memory at the specified address and then verify. legend: tbd = to be determined note 1: one row of code memory consists of (32) 24-bit words. refer to table 2-3 for device-specific information. pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 35 5.2.4 command descriptions the commands supported by the programming executive are described in section 5.2.5 ?scheck command? through section 5.2.13 ?qver command? . 5.2.5 scheck command the scheck command instructs the programming executive to merely generate a response. this command is used as a ?sanity check? to verify if the programming executive is operational. expected response (2 words): 1000h 0002h 5.2.6 readc command the readc command instructs the programming executive to read n or device id registers, starting from the 24-bit address specified by addr_msb and addr_ls. when this command is used to read the device id registers, the upper byte in every data word returned by the programming executive is 00h and the lower byte contains the device id register value. expected response (4 + 3 * (n ? 1)/2 words for n odd): 1100h 2 + n device id register 1 ... device register n 5.2.7 readd command the readd command instructs the programming executive to read n 16-bit words from data eeprom memory, starting from the 24-bit address specified by addr_msb and addr_ls. expected response (n + 2 words): 1e00h 2 + n data word 1 ... data word n 15 12 11 0 opcode length field description opcode 0h length 1h note: this instruction is provided for development purposes only; this is not required for programming. 15 12 11 8 7 0 opcode length naddr_msb addr_ls field description opcode 1h length 3h n number of 8-bit device id registers to read (max. of 256). addr_msb msb of 24-bit source address. addr_ls least significant 16 bits of 24-bit source address. note: this command can only be used to read 8-bit or 16-bit data. note: reading unimplemented memory will cause the programming executive to reset. ensure that only memory locations present on a particular device are accessed. 15 12 11 8 7 0 opcode length reserved0 n reserved1 addr_msb addr_ls field description opcode eh length 4h reserved0 0h n number of 16-bit words to read (max of 256). reserved1 0h addr_msb msb of 24-bit source address. addr_ls least significant 16 bits of 24-bit source address. note: this command can only be used to read 16-bit data. pic24fxxkaxxx ds39919a-page 36 advance information ? 2008 microchip technology inc. 5.2.8 readp command the readp command instructs the programming executive to read n 24-bit words of code memory, including configuration registers, starting from the 24-bit address specified by addr_msb and addr_ls. the entire data returned in response to this command uses the packed data format described in section 5.2.2 ?packed data format? . expected response (2 + 3 * n/2 words for n even): 1200h 2 + 3 * n/2 lsb program memory word 1 ... lsb data word n expected response (4 + 3 * (n ? 1)/2 words for n odd): 1200h 4 + 3 * (n ? 1)/2 lsb program memory word 1 ... msb of program memory word n (zero-padded) 5.2.9 progc command the progc command instructs the programming executive to program a single user id register located at the specified memory address. after the specified data word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. expected response (2 words): 1400h 0002h 5.2.10 progd command the progd command instructs the programming executive to program one word (16-bit) of data eeprom memory, starting from the 24-bit address specified by addr_msb and addr_ls. once one word of data eeprom has been programmed, the programming executive verifies the programmed data against the data in the command. 15 12 11 8 7 0 opcode length n reserved addr_msb addr_ls field description opcode 2h length 4h n number of 24-bit instructions to read (max. of 32768). reserved 0h addr_msb msb of 24-bit source address. addr_ls least significant 16 bits of 24-bit source address. note: this command can only be used to read 24-bit data. note: reading unimplemented memory will cause the programming executive to reset. ensure that only memory locations present on a particular device are accessed. 15 12 11 8 7 0 opcode length reserved addr_msb addr_ls data field description opcode 4h length 4h reserved 0h addr_msb msb of 24-bit destination address. addr_ls least significant 16 bits of 24-bit destination address. data 8-bit data word. 15 12 11 8 7 0 opcode length reserved addr_msb addr_ls d_1 field description opcode fh length 4h reserved 0h addr_msb msb of 24-bit source address. addr_ls least significant 16 bits of 24-bit source address. d_1 16-bit data word. pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 37 expected response (2 words): 1f00h 0002h 5.2.11 progp command the progp command instructs the programming executive to program one row of code memory to the specified memory address. programming begins with the row address specified in the command. the destination address should be a multiple of 40h. the data to program to memory, located in command words, d_1 through d_48, should be arranged using the packed instruction word format depicted in figure 5-5. after the entire data is programmed to code memory, the programming executive verifies the programmed data against the data in the command. the progp command is also used to program configuration words. while progp is used to program configuration words, the length in the command should be four. only one configuration word at a time can be programed. the unimplemented bits of the configuration word should be stuffed with ? 1 ?s. expected response (2 words): 1500h 0002h 5.2.12 qblank command the qblank command queries the programming exec- utive to determine if the contents of code memory and code-protect configuration bits (gcp and gwrp) are blank (contain all ? 1 ?s). the size of the code memory to check should be specified in the command. the blank check for code memory begins at 0h and advances toward larger addresses for the specified number of instruction words. qblank returns a qe_code of f0h if the specified code memory and code-protect bits are blank; otherwise, it returns a qe_code of 0fh. expected response (2 words for blank device): 1af0h 0002h expected response (2 words for non-blank device): 1a0fh 0002h note: refer to table 2-4 for data eeprom memory size information. 15 12 11 8 7 0 opcode length reserved addr_msb addr_ls d_1 d_2 ... d_48 field description opcode 5h length 33h reserved 0h addr_msb msb of 24-bit destination address. addr_ls least significant 16 bits of 24-bit destination address. d_1 16-bit data word 1. d_2 16-bit data word 2. ... 16-bit data word 3 through 47. d_48 16-bit data word 48. note: refer to table 2-3 for code memory size information. 15 12 11 0 opcode length psize reserved dsize field description opcode ah length 3h psize length of program memory to check in 24-bit words (max. of 49152). reserved 0h dsize length of data memory to check in 16-bit words (max. of 2048). note: qblank does not check the system operation configuration bits as these bits are not set to ? 1 ? when a chip erase is performed. pic24fxxkaxxx ds39919a-page 38 advance information ? 2008 microchip technology inc. 5.2.13 qver command the qver command queries the version of the programming executive software stored in the test memory. the ?version.revision? information is returned in the response?s qe_code using a single byte in the following format: main version in upper nibble and revision in the lower nibble (i.e., 23h stands for version 2.3 of the programming executive software). expected response (2 words): 1bmnh (?mn? stands for version m.n) 0002h 5.3 programming executive responses the programming executive sends a response to the programmer for each command that it receives. the response indicates if the command was processed correctly. it includes any required response data or error data. the programming executive response set is provided in table 5-2. this table contains the opcode, mnemonic and description for each response. the response format is described in section 5.3.1 ?response format? . table 5-2: programming executive response opcodes 5.3.1 response format all programming executive responses have a general format consisting of a two-word header and any required data for the command. 5.3.1.1 opcode field the opcode is a 4-bit field in the first word of the response. the opcode indicates how the command was processed (see table 5-2). if the command was processed successfully, the response opcode is pass; if there was an error in processing the command, the response opcode is fail and the qe_code indicates the reason for the failure. if the command sent to the programming executive is not identified, the programming executive returns a nack response. 5.3.1.2 last_cmd field the last_cmd is a 4-bit field in the first word of the response and it indicates the command that the programming executive processed. as the program- ming executive can process only one command at a time, this field is technically not required. however, it can be used to verify if the programming executive correctly received the command that the programmer transmitted. 15 12 11 0 opcode length field description opcode bh length 1h opcode mnemonic description 1h pass command successfully processed. 2h fail command unsuccessfully processed. 3h nack command not known. field description opcode response opcode. last_cmd programmer command that generated the response. qe_code query code or error code. length response length in 16-bit words (includes 2 header words). d_1 first 16-bit data word (if applicable). d_n last 16-bit data word (if applicable). 15 12 11 8 7 0 opcode last_cmd qe_code length d_1 (if applicable) ... d_n (if applicable) pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 39 5.3.1.3 qe_code field the qe_code is a byte in the first word of the response. this byte is used to return data for query commands and error codes for all of the other commands. when the programming executive processes one of the two query commands ( qblank or qver ), the returned opcode is always pass and the qe_code holds the query response data. table 5-3 provides the format of the qe_code for both queries. table 5-3: qe_code for queries when the programming executive processes any command other than a query, the qe_code represents an error code. table 5-4 provides the supported error codes. if a command is successfully processed, the returned qe_code is set to 0h, which indicates that there was no error in the command processing. if the verify of the programming for the progp or progc command fails, the qe_code is set to 1h. for all other programming executive errors, the qe_code is 2h. table 5-4: qe_code for non-query commands 5.3.1.4 response length the response length indicates the length of the programming executive?s response in 16-bit words. this field includes the two words of the response header. with the exception of the response for the readp command, the length of each response is only two words. the response to the readp command uses the packed instruction word format described in section 5.2.2 ?packed data format? . when reading an odd number of program memory words (n odd), the response to the readp command is (3 * (n + 1)/2 + 2) words. when reading an even number of program memory words (n even), the response to the readp command is (3 * n/2 + 2) words. 5.4 programming the programming executive to memory this section describes the programming of the programming executive to memory and also provides the procedure to perform this. 5.4.1 overview if it is determined that the programming executive is not present in the executive memory (as described in section 4.2 ?confirming the presence of the programming executive? ), it must be programmed into the executive memory using icsp, as described in section 3.0 ?device programming ? icsp? . storing the programming executive to executive memory is the same as normal programming of code memory: the executive memory should be erased and then the programming executive must be programmed 32 words at a time. erasing the last eight words causes the device diagnostic data in the diagnostic words at addresses 8007f0h to 8007feh to be erased. in order to retain these, the memory locations should be read and stored, and then be reprogrammed in the last eight words of program memory. table 5-5 provides this control flow. query qe_code qblank 0fh = code memory is not blank f0h = code memory is blank qver 0xmn, where programming executive software version = m.n (i.e., 32h stands for version 3.2 of the programming executive software) qe_code description 0h no error. 1h verify failed. 2h other error. pic24fxxkaxxx ds39919a-page 40 advance information ? 2008 microchip technology inc. table 5-5: programming th e programming executive command (binary) data (hex) description step 1: exit reset vector and erase the executive memory. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize pointers to read diagnostic words for storage in w6-w13. 0000 0000 0000 0000 0000 200800 880190 207f00 2000c2 000000 mov #0x80, w0 mov w0, tblpag mov #0x07f0, w1 mov #0xc, w2 nop step 3: repeat this step eight times to read diagnostic words, storing them in w registers, w6-w13. 0000 0000 0000 ba1931 000000 000000 tblrdl [w1++],[w2++] nop nop step 4: initialize the nvmcon to erase the executive memory. 0000 0000 2405a0 883b00 mov #0x405a, w0 mov w0, nvmcon step 5: initiate the erase cycle. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 200800 880190 200001 000000 bb0881 000000 000000 a8e761 000000 000000 mov #0x80, w0 mov w0, tblpag mov #0x00, w1 nop tblwtl w1, [w1] nop nop bset nvmcon, #15 nop nop step 6: repeat this step to poll the wr bit (bit 15 of nvmcon) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0000 0001 0000 040200 000000 803b02 883c22 000000 000000 pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 41 step 10: load w0:w2 with the next two words of packed programming executive code. 0000 0000 0000 2 pic24fxxkaxxx ds39919a-page 42 advance information ? 2008 microchip technology inc. 5.5 programming verification after the programming executive is programmed to the executive memory using icsp, it must be verified. verify by reading out the contents of the executive memory and comparing it with the image of the programming executive stored in the programmer. read the contents of the executive memory using the same method described in section 3.9 ?reading code memory? . table provides the procedure for reading the executive memory. step 18: load the saved diagnostic words in last eight write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 bb1a86 000000 000000 bb1a87 000000 000000 bb1a88 000000 000000 bb1a89 000000 000000 bb1a8a 000000 000000 bb1a8b 000000 000000 bb1a8c 000000 000000 bb1a8d 000000 000000 tblwtl w6, [w5++] nop nop tblwtl w7, [w5++] nop nop tblwtl w8, [w5++] nop nop tblwtl w9, [w5++] nop nop tblwtl w10, [w5++] nop nop tblwtl w11, [w5++] nop nop tblwtl w12, [w5++] nop nop tblwtl w13, [w5++] nop nop step 19: repeat steps 13 through 15. table 5-5: programming the programming executive (continued) command (binary) data (hex) description note: in step 2 of table 5-6, the tblpag register is set to 80h, such that the executive memory may be read. pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 43 table 5-6: reading executive memory command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 000000 040200 000000 nop goto 0x200 nop step 2: initialize tblpag and the read pointer (w6) for tblrd instruction. 0000 0000 0000 200800 880190 eb0300 mov #0x80, w0 mov w0, tblpag clr w6 step 3: initialize the write pointer (w7) to point to the visi register. 0000 0000 207847 000000 mov #visi, w7 nop step 4: read and clock out the contents of the next two locations of the executive memory through the visi register using the regout command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 ba1b96 000000 000000 pic24fxxkaxxx ds39919a-page 44 advance information ? 2008 microchip technology inc. 6.0 device id the device id region of memory can be used to determine the mask, variant and manufacturing information about the device. the device id region is 2 x 16 bits and it can be read using the readc command. this region of memory is read-only and can also be read when code protection is enabled. table 6-1 provides the device id for each device; table 6-2 provides the device id registers; table 6-3 describes the bit field of each register. table 6-1: device ids 6.1 checksums 6.1.1 checksum computation checksums for the pic24fxxkaxxx family are 16 bits. the checksum is calculated by summing the following: ? contents of the code memory locations ? contents of the configuration registers table 6-4 describes how to calculate the checksum for each device. all memory locations are summed, one byte at a time, using only their native data size. more specifically, configuration registers are summed by adding the lower two bytes of these locations (the upper byte is ignored) while the code memory is summed by adding all three bytes of the code memory. table 6-2: pic24fxxkaxxx device id registers device id devid PIC24F08KA101 0d08h pic24f16ka101 0d01h pic24f08ka102 0d0ah pic24f16ka102 0d03h pic24f04ka200 0d02h pic24f04ka201 0d00h address name bit 15 14131211109876543210 ff0000h devid famid<7:0> dev<7:0> ff0002h devrev ? rev<3:0> table 6-3: device id bits description bit field register description famid<7:0> devid encodes the family id of the device. dev<7:0> devid encodes the individual id of the device. rev<3:0> devrev encodes the revision number of the device. table 6-4: checksum computation device read code protection checksum computation erased checksum value chip checksum with 0xaaaaaa at 0x00 location and at last location pic24f16kaxxx disabled cfgb + sum (0:002bfe) 0xc334 0xc136 enabled 0 0x0000 0x0000 pic24f08kaxxx disabled cfgb + sum (0:0015fe) 0xe434 0xe236 enabled 0 0x0000 0x0000 pic24f04kaxxx disabled cfgb + sum (0:000afe) 0x74b4 0x72b6 enabled 0 0x0000 0x0000 legend: item description sum[a:b] = byte sum of locations, a to b inclusive (all 3 bytes of code memory) cfgb = configuration block (masked), byte sum of (fbs & 0x000f + fgs & 0x0003 + foscsel & 0x0087 + fosc & 0x00df + fwdt & 0x00df + fpor & 0x00fb + ficd & 0x00c3 + fds & 0x00ff) pic24fxxkaxxx ? 2008 microchip technology inc. advance information ds39919a-page 45 7.0 ac/dc characteristics and timing requirements table 7-1: standard operating conditions standard operating conditions operating temperature: 0 c to +70 c and programming: +25 c is recommended. param no. symbol characteristic min max units conditions d111 v dd supply voltage during programming v ddcore 3.60 v normal programming d112 i pp programming current on mclr ?50 a? d113 i ddp supply current during programming ? 2 ma ? d031 v il input low voltage v ss 0.2 v dd v? d041 v ih input high voltage 0.8 v dd v dd v? d042 v ihh programing voltage on v pp v dd +1.5 9 v ? d080 v ol output low voltage ? 0.4 v i ol = 8.5 ma @ 3.6v d090 v oh output high voltage 1.4 ? v i oh = -3.0 ma @ 3.6v d012 c io capacitive loading on i/o pin (pgdx) ? 50 pf to meet ac specifications p1 t pgc serial clock (pgcx) period 125 ? ns ? p1a t pgcl serial clock (pgcx) low time 50 ? ns ? p1b t pgch serial clock (pgcx) high time 50 ? ns ? p2 t set 1 input data setup time to serial clock 15 ? ns ? p3 t hld 1 input data hold time from pgcx 15 ? ns ? p4 t dly 1 delay between 4-bit command and command operand 40 ? ns ? p4a t dly 1 a delay between 4-bit command operand and the next 4-bit command 40 ? ns ? p5 t dly 2 delay between last pgcx of command byte and first pgcx of read of data word 20 ? ns ? p6 t set 2v dd setup time to mclr 100 ? ns ? p7 t hld 2 input data hold time from mclr v pp (from v ihh to v ih ) 25 ? ms ? p8 t dly 3 delay between last pgcx of command byte and pgdx by programming executive 12 ? s? p9 t dly 4 programming executive command processing time 40 ? s? p10 t dly 6 pgcx low time after programming 400 ? ns ? p11 t dly 7 chip erase time 5 ? ms ? p12 t dly 10 page (4 rows) erase time 5 ? ms ? p13 t dly 9 row programming time 2 ? ms ? p14 t r mclr rise time to enter icsp? mode ? 1.0 s? p15 t valid data out valid from pgcx 10 ? ns ? p16 t dly 10 delay between last pgcx and mclr 0?s ? p17 t hld 3mclr to v dd ?100ns ? p18 t key 1 delay between first mclr and first pgcx for key sequence on pgdx 40 ? ns ? p19 t key 2 delay between last pgcx for key sequence on pgdx and second mclr 1?ms ? pic24fxxkaxxx ds39919a-page 46 advance information ? 2008 microchip technology inc. p20 t dly 11 delay between pgdx by programming executive and first pgcx of reception of response 23 ? s? p21 t dly 12 delay between programming executive command response words 8?ns ? table 7-1: standard operating conditions (continued) standard operating conditions operating temperature: 0 c to +70 c and programming: +25 c is recommended. param no. symbol characteristic min max units conditions ? 2008 microchip technology inc. advance information ds39919a-page 47 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds39919a-page 48 advance information ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 |
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